Method and apparatus for address allotting and verification in a semiconductor device

ABSTRACT

A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

CROSS-REFERENCES TO RELATED APPLICATIONS

This is a continuation application of International Application No.PCT/JP2005/001083 filed Jan. 27, 2005, which was not published inEnglish under PCT Article 21(2).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor devices, andmore particularly, to a semiconductor device that includes anon-volatile memory. Even more specifically, the present inventionrelates to a technique of controlling the operation of a semiconductordevice using CAM (Content Addressable Memory) data.

2. Description of the Related Art

Conventionally, two types of non-volatile memory semiconductor devicesare well known: one has a structure that determines whether the datastored in a non-volatile memory is equivalent to expected value data soas to automatically perform data checking at the time of programming orerasing a non-volatile memory and the other one has a structure that hasregular non-volatile memory cells to be used by users and CAM cells tocontrol the operation of the semiconductor device. In recent years, soas to reduce the device size, a structure that has CAM cells formed withregular non-volatile memory cells has been proposed. If the CAM cellshave the same structures as the regular memory cells, the word lines andthe bit lines to be connected to the CAM cells should preferably havethe same structure as those to be connected to the regular memory cells.

The CAM data that is written in CAM cells having the same structures asregular memory cells is preferably read out and transferred to avolatile memory unit (a latch circuit) such as a SRAM (Static RandomAccess Memory) at the time of power on or resetting of the hardware. Bydoing so, the operating speed at the time of read-access to the regularnon-volatile memory cells is not reduced by CAM data reading.

If the CAM cells have the same structure as the regular memory cells,the verifying operation of the CAM cells should preferably be completedwithin the memory device at the time of rewriting the CAM data, like theverifying operation of the regular memory cells. Japanese UnexaminedPatent Publication No. 6-76586 discloses a verification circuit forprogramming regular memory cells.

When regular memory cells are to be programmed, the information “1” or“0” is input through I/Os by a user. A memory cell having theinformation “0” input thereto is a memory cell to be programmed, and amemory cell having the information “1” input thereto is a memory cell tobe erased. The information of each I/O is used as an expected value atthe time of verification.

In a semiconductor device, prior to actual programming, the data is readout from the memory cell connected to the word lines to be programmed.This process is referred to as “pre-reading”. The pre-read data iscompared with the data input through the I/Os. According to thecomparison results, programming is performed only on the memory cellsthat are in the erased state (holding the information “1”) and are to beprogrammed through the I/Os (having the information “0” input thereto).

Programming is not performed on the already programmed memory cells(holding the information “0”), because additional programming results instress. If the information that is input to the already programmedmemory cells (holding the information “0”) through the I/Os is “1”, anerror signal is returned to the controller. This is because the memorycells are non-volatile memories that physically perform writingoperations, and have non-volatility. Therefore, an erasing operation isindependent of a programming operation, and erasing is collectivelyperformed on one sector. If the information that is input through theI/Os to the already erased memory cells (holding the information “1”) is“1”, no operations are performed.

Programming of CAM cells should preferably be performed in the samemanner as the programming of regular memory cells. For programming CAMcells, there is a method that involves two different interfaces from theprogramming interface for regular memory cells. Input setting isperformed in accordance with the information “1” and the information “0”input through the I/Os so as to determine CAM cells to be programmed andCAM cells not to be programmed (see Japanese Unexamined PatentPublication No. 10-106275). The programming interface for the inputsetting is referred to as “interface 1”. In the case of interface 1, auser inputs the information “1” and the information “0” through therespective I/Os. The information “1” indicates a memory cell to beprogrammed, while the information “0” indicates a memory cell for whichno operation is to be performed (i.e., not to be programmed).

For programming CAM cells, there is not only the method involvinginterface 1, but also a method of designating only the CAM cells to beprogrammed through command input. The programming interface used in thismethod is referred to as “interface 2”. In the case of using interface2, the addresses of CAM cells are designated, and the address-designatedCAM cells are to be programmed.

Each CAM cell should preferably have a user block in which users canrewrite information and a factory block in which the vender maker writesinformation in advance. If the CAM data in the user block are rewrittenin this structure, it is necessary to protect the memory cells in thefactory block from disturb caused by cell information. “Disturb” is aphenomenon in which charge loss or charge gain occurs in memory cellsdue to electric influence from the word lines and bit lines to which thememory cells are connected at the time of programming the designatedmemory cells.

In a case where the CAM data in the user block is to be rewritten, it isnecessary to protect the memory cells in the factory block from disturbcaused by the cell information. However, there is not a conventionaltechnique for satisfying this requirement, which is the first problemwith the prior art.

The second problem with the prior art is that proper verification cannotbe performed after programming CAM cells. The following is a descriptionof this problem.

This second problem is caused when a verifying operation is performedsimultaneously on CAM cells coupled to the same word line in an arraystructure which has more than one CAM cell connected to a word line.

FIG. 1A illustrates CAM cells that are connected to one word line andare in a programmed state. The CAM cells of “1” in FIG. 1A are erasedcells and have not been programmed. The CAM cells of “0” are programmedcells and have already been programmed.

In FIG. 1B, I/O input by interface 1 is performed on the CAM cells onthe word line shown in FIG. 1A. Here, the CAM cells with “1” are to beprogrammed, and the cells with “0” are not to be programmed and remainin the current state.

In the semiconductor device, the data that is pre-read from CAM cells onthe same word line are compared with the data that is input through theI/Os. According to the comparison results, programming is performed onlyon the CAM cell that is in the erased state (with the information “1”being stored) and is to be I/O-programmed (with the information “1”being input). In this example, programming is performed on the rightmostCAM cell on the word line, as shown in FIG. 1C.

Verification is performed after the programming. The data that is readout from the CAM cells after the programming is compared with theI/O-input data as expected values (see FIG. 1D). At this point, if anI/O-input expected value indicates “non-programming” for an alreadyprogrammed CAM cell, the comparison result is “fail”, and the verifyingoperation ends in failure.

In the case where the above described designation method involvinginterface 2 is employed, only the CAM cells to be programmed aredesignated by a command input. Therefore, the expected valuescorresponding to the CAM cells not programmed on the same word linecannot be produced, and a verifying operation cannot be done.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide asemiconductor device and an address allocation method and a verificationmethod therefore in which the above disadvantages are eliminated.

Amore specific object of the present invention is to provide asemiconductor device having CAM cells on which data rewrite andverification can be properly performed, and an address allocation methodand a verification method therefor.

To achieve the above object of the present invention, a semiconductordevice of the present invention includes a cell array that storesoperation setting information for the semiconductor device and a controlunit that controls read and write operations to be performed on the cellarray. The control unit allocates different row addresses for respectivefunctions of the operation setting information. As the different rowaddresses are allocated to the respective functions of the operationsetting information, stress (gate disturb) is not caused in the cellarray of unselected functions at the time of programming.

In the above semiconductor device, the control unit may also allocatedifferent column addresses for the respective functions of the operationsetting information. As the different column addresses are allocated tothe respective functions of the operation setting information, stress(drain disturb) is not caused in the cell array of unselected functionsat the time of programming.

In the above semiconductor device, the control unit may allocatecontinuous column addresses for the respective functions of theoperation setting information. As the continuous column addresses areallocated for the respective functions, the data can be read outsuccessively, and reading time can thus be shortened.

In the above semiconductor device, the control unit may further allocatethe operation setting information to column addresses selected by one ofthe row addresses. Alternatively, the control unit allocates theoperation setting information to all I/Os of an arbitrary columnselected by the row address. In this manner, the number of readingcycles can be minimized, thereby reducing reading time.

In the above semiconductor device, memory cells accessed by differentrow addresses are isolated from each other. Since the line pattern oflocal bit lines is cut off between the memory cells of different rowaddresses, the data can be read out simply by switching columnaddresses, with a word line being selected between memory cells ofrespective functions.

In the above semiconductor device, memory cells may be connected toswitches for selectively connecting the memory cells to bit linesarranged on a corresponding column. With this structure, the data can beread out simply by switching column addresses, with a word line beingselected between memory cells of respective functions.

In the above semiconductor device, the cell array further includes cellsfor each column, and memory cells not storing the operation settinginformation are isolated from bit lines arranged on a correspondingcolumn. Accordingly, stress is not caused in the cell array ofunselected functions at the time of programming.

In the above semiconductor device, the control unit may also select allword lines on the cell array, and read the operation setting informationfrom the cell array while successively changing the column addresses.With this structure, the data can be read out simply by switching columnaddresses without switching word lines and the reading time cantherefore be shortened.

In the above semiconductor device, the control unit may include a tablethat converts the number of a designated memory cell into an address ofa corresponding memory cell. Since a designated memory cell number canbe converted into the address of the designated cell, programming canthen be performed on the desired cell.

The present invention also provides a method of allocating addresses toa cell array that stores operation setting information as to asemiconductor device. This method includes the step of allocatingdifferent row addresses to respective functions of the operation settinginformation. Since different row addresses are allocated to therespective functions of the operation setting information, stress is notcaused in the cell array of unselected functions at the time ofprogramming. Also, erasing can be performed for each function.

This method further includes the step of allocating different columnaddresses for the respective functions of the operation settinginformation. By this method, the data can be read out with differentcolumn addresses for the respective functions of the operation settinginformation.

This method further includes the step of allocating continuous columnaddresses for the respective functions of the operation settinginformation. By this method, the operation setting information ofrespective functions can be readily read out.

This method further includes the step of selecting all word lines on thecell array and successively changing the column addresses to read datafrom the cell array. Accordingly, the operation setting information canbe read out simply by switching the column addresses, without switchingword lines.

The present invention also provides a semiconductor device that includesa cell array that stores the operation setting information as to thesemiconductor device, a write circuit that simultaneously programsmemory cells in the cell array, and a verification circuit that verifiesa programming result of only a memory cell that is actually programmed.In this manner, only the programming results of the actually programmedcell need be verified.

In the above semiconductor device, the verification circuit includescomparator circuits that compare expected value data obtained by normalprogramming with data that is read from the memory cells afterprogramming and a control unit that makes a pseudo-pass for comparatoroutputs related to programming results of memory cells that are notprogrammed. In this manner, a control operation is performed to make apseudo-pass for the programming results from the comparator circuitsallocated to unprogrammed cells. Accordingly, the programming result ofthe programmed cell can be reflected in the verification.

In the above semiconductor device, the control unit identifies a memorycell in an erased state prior to the programming, the memory cell beingdesignated as to be programmed by an external input, and thesemiconductor device further includes a circuit that generates expectedvalue data obtained by normal programming in response to an instructionfrom the control unit, outputting the expected value data to one of thecomparator circuits related to the designated memory cell. In thismanner, the actual programmed cell is detected and the expected valuedata is output to the comparator circuit allocated to the cell. Thus,the programming result of the programmed cell can be accuratelydetermined.

The present invention also provides a semiconductor device that includesa cell array that stores operation setting information as to thesemiconductor device, a write circuit that simultaneously programsmemory cells in the cell array, a volatile memory circuit that storesdata stored in the memory cells prior to programming, and a verificationcircuit that verifies, with the data stored in the volatile memorycircuit, a memory cell that is not programmed, and verifies anothermemory cell that is actually programmed with expected value dataobtained by normal programming. In this manner, verification isperformed on unprogrammed cells using the stored data. For an actuallyprogrammed cell, the programming result is verified using the expectedvalue data obtained when programming is properly performed. Thus, theprogramming result of the programmed cell can be accurately verified.

In the above semiconductor device, the verification circuit may alsoinclude comparator circuits that compare expected value data obtained bynormal programming with data that is read from the memory cells or asense amplifier after programming and a control unit that identifies thememory cell that is actually programmed and causes one of the comparatorcircuits related to the memory cell actually programmed to verify aprogramming result thereof with the expected value data obtained bynormal programming. With this structure, the actually programmed cell isidentified and the programming result of the programmed cell can beaccurately verified.

In the above semiconductor device, the control unit identifies a memorycell in an erased state prior to programming, the memory cell beingdesignated as to be programmed by an external input, and thesemiconductor device further includes a circuit that changes theexpected value data stored in the volatile memory circuit and related toa memory cell in an erased state prior to programming to the expectedvalue data obtained by normal programming, ouputting the expected datavalue thus changed to one of the comparator circuits. With thisstructure, the actually programmed cell is identified, and theprogramming result of the programmed cell can be accurately verified.

In the above semiconductor device, the control unit externally receivesan instruction signal indicating whether each memory cell should beprogrammed and identifies a memory cell to be actually programmed bydetermining whether the memory cell to be programmed is in an erasedstate. With this structure, a cell to be programmed is identified by anexternal instruction signal, and programming is performed on theidentified cell.

In the above semiconductor device, the control unit decodes addressinformation externally supplied to identify a memory cell to beprogrammed, the control unit identifying a memory cell to be actuallyprogrammed by determining whether the memory cell to be programmed is inan erased state. With this structure, a cell to be programmed isidentified with externally input address information and programming isperformed on the identified cell.

In the above semiconductor device, the control unit changes an interfacethat designates a memory cell to be programmed in response to a modeswitching signal that is externally supplied. With this structure, acell to be programmed can be designated in accordance with interfaces.

In the above semiconductor device, the verification circuit is sharedbetween verification after programming of the cell array storing theoperation setting information and verification after programming of aregular cell array storing regular data. With this structure, theverification functions can be shared, being performed by oneverification circuit. Accordingly, the circuit size of the semiconductordevice can be reduced.

In the above semiconductor device, the comparator circuits compare theexpected value data obtained by normal programming with data read fromthe memory cells after programming in response to a mode signal forswitching an operation mode to programming of the cell array storing theoperation setting information. With this structure, the comparatorcircuits operate only at the time of verification.

In the above semiconductor device, the comparator circuits use outputsof the volatile memory circuit at the time of programming of the cellarray storing the operation setting information and the comparatorcircuits use outputs of a circuit holding the expected value dataobtained by normal programming of the memory cell at the time ofprogramming a regular cell. With this structure, different controloperations can be performed for verification between the programming ofthe cell array that stores the operation setting information and theprogramming of the regular cell array.

The present invention also provides a method of verifying a cell arraythat stores the operation setting information as to a semiconductordevice. This method includes the step of verifying a programming resultof only a memory cell that is actually programmed among memory cells inthe cell array. By this method, only the programming result of theactually programmed cell need be verified.

The present invention also provides a method of verifying a cell arraythat stores the operation setting information as to a semiconductordevice. This method includes the steps of verifying a memory cell thatis not programmed with data stored in the memory cell prior toprogramming and verifying another memory cell that is actuallyprogrammed with expected value data obtained by normal programming. Bythis method, verification is performed on unprogrammed cells, using thestored data. Thus for an actually programmed cell, the programmingresult is verified using the expected value data that is obtained whenprogramming is properly performed. Therefore, the programming result ofthe programmed cell can be accurately verified.

With any of the above semiconductor devices each having a cell arraythat stores the operation setting information, data rewrite andverification can properly be performed.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention willbecome more apparent from the following detailed description when readin conjunction with the accompanying drawings, in which:

FIGS. 1A through 1D illustrate problems with the prior art;

FIG. 2 illustrates the structure of a semiconductor device in accordancewith a first embodiment of the present invention;

FIG. 3 illustrates an example bitmap of a CAM cell array in accordancewith the first embodiment of the present invention;

FIG. 4 illustrates an example bitmap of a CAM cell array in accordancewith the first embodiment of the present invention;

FIG. 5 shows the correspondence between the WP bit numbers and theaddresses in accordance with the first embodiment of the presentinvention;

FIG. 6 shows the conversion of the WP addresses into the addresses ofthe CAM cell array in accordance with the first embodiment of thepresent invention;

FIGS. 7A and 7B illustrate the memory cell structures of a CAM cellarray and a regular cell array in accordance with the first embodimentof the present invention;

FIGS. 8A and 8B illustrate the memory cell structures of a CAM cellarray and a regular cell array in accordance with the first embodimentof the present invention;

FIG. 9 illustrates the structures of logic circuits that convert WPaddresses into CAM column addresses in accordance with the firstembodiment of the present invention;

FIG. 10 illustrates the structures of logic circuits that convert WPaddresses into DQs in accordance with the first embodiment of thepresent invention;

FIG. 11 illustrates the structures of a cell array and a verificationcircuit in accordance with a second embodiment of the present invention;

FIG. 12 illustrates the structure of a WP bit select circuit inaccordance with the second embodiment of the present invention;

FIG. 13 is a flowchart of the operation of the verification circuit inthe I/O mode in accordance with the second embodiment of the presentinvention;

FIGS. 14A through 14D illustrate the procedures to be carried out by theverification circuit in the I/O mode in accordance with the secondembodiment of the present invention;

FIG. 15 is a flowchart of the operation of the verification circuit inthe address mode in accordance with the second embodiment of the presentinvention;

FIG. 16 illustrates the procedures to be carried out by the verificationcircuit in the address mode in accordance with the second embodiment ofthe present invention;

FIG. 17 illustrates, in greater detail, the structure of theverification circuit in accordance with the second embodiment of thepresent invention;

FIG. 18 illustrates the structures of a cell array and a verificationcircuit in accordance with a third embodiment of the present invention;

FIG. 19 illustrates the structure of a WP bit select circuit inaccordance with the third embodiment of the present invention;

FIG. 20 is a flowchart of the operation of the verification circuit inthe I/O mode in accordance with the third embodiment of the presentinvention;

FIG. 21 illustrates the procedures to be carried out by the verificationcircuit in the I/O mode in accordance with the third embodiment of thepresent invention;

FIG. 22 is a flowchart of the operation of the verification circuit inthe address mode in accordance with the third embodiment of the presentinvention;

FIG. 23 illustrates the procedures to be carried out by the verificationcircuit in the address mode in accordance with the third embodiment ofthe present invention; and

FIG. 24 illustrates, in greater detail, the structure of theverification circuit in accordance with the third embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following is a description of preferred embodiments of the presentinvention, with reference to the accompanying drawings.

First Embodiment

Referring first to FIG. 2, the structure of this embodiment isdescribed. A semiconductor device 1 in accordance with this embodimentincludes a regular cell array 3 that stores regular data and a CAM cellarray 4 that stores CAM data. The regular cell array 3 and the CAM cellarray 4 constitute a cell array unit 2. The CAM cell array 4 is formedwith memory cells disposed on multiple rows and columns like the regularcell array 3. The CAM cell array 4 stores the operation settinginformation (so-called CAM data) for the semiconductor device 1. Forexample, the write protect information for the regular cell array 3, theinternal voltage control information for the semiconductor device 1, theinternal timing control information, the operation mode switchinformation, and the memory cell redundant bit information are stored inthe CAM cell array 4. The semiconductor device 1 also includes aperipheral circuit that performs data write, read, and erase on the cellarrays. As shown in FIG. 1, the peripheral circuit includes a rowdecoder 5, a column decoder 6, a command register 7, a controller 8, aprogram voltage generating circuit 9, a sense amplifier 10, a volatilememory unit 11, a determining unit 12, a verification circuit 13, and adata input/output circuit 14.

The row decoder 5 selectively drives word lines WL, based on therespective addresses, at the time of writing, erasing, or reading data.A predetermined voltage is applied to the word line driver (not shown)from the program voltage generating circuit 9. The column decoder 6selects a column from the cell array, i.e., a global bit line or a localbit line, based on an externally input address.

The command register 7 decodes an external command to generate aninternal control signal. The controller 8 controls the internaloperation, in response to the internal control signal decoded by thecommand register 7. The controller 8 is formed with a microprocessor,for example, and controls the program voltage generating circuit 9, thedetermining circuit 12, and the verification circuit 13.

The CAM data stored in the CAM cell array 4 is transferred to and storedin the volatile memory unit 11 at the time of switching on thesemiconductor device 1 or resetting the hardware. With the CAM databeing read into the volatile memory unit 11, a delay during a readingoperation can be prevented when the CAM data is read out of the volatilememory 11 at the time of read-accessing the regular cell array 3. Thereading operation period should preferably be short, because theactivating period becomes longer unless the CAM data is transferred in ashort time.

The data input/output circuit 14 includes an I/O terminal that inputs aprogram instruction from the outside and outputs readout data. The datainput/output circuit 14 performs data write (programming) and read onthe CAM cell array 4.

Next, the structure of the CAM cell array 4 is described. FIG. 3 shows abitmap illustrating the allocation of the CAM data to the CAM cell array4. The CAM cell array 4 is divided into function blocks including a userblock and a factory block. Data erase may be performed in each functionblock.

A “user block” is a write region in which a user writes a write-protectbit (hereinafter also referred to as “WP bit”) or the like. A“write-protect” bit is a bit for controlling the programming or erasingof memory cells, and a unit write-protect bit is formed with anarbitrary number of sectors (hereinafter, the unit will be referred toas the “sector group”). In the example illustrated in FIG. 3, WP bitsare preferably allocated to all the I/Os DQ0 through DQ15. A word line(a row address) and four local bit lines (LBL), i.e., four columnaddresses (LBL0 through LBL3), are allocated to each one I/O, and aglobal bit line (GBL), GBL0, is allocated to one I/O. Here, theallocation of the WP bits to all the I/Os DQ0 through DQ15 is toallocate data to all the memory cell of a column selected by a rowaddress. If the number of WP bits is not an integer divisible by thenumber of I/Os, emphasis may be put on I/O allocation in columnallocation, or emphasis may be put on column allocation in I/Oallocation. For example, if the number of WP bits is 60 and the numberof I/Os is 16, I/Os (DQ) corresponding to the WP bits 60, 61, 62, and 63of the last column address (000011) are not allocated, or the I/Os (DQ)corresponding to the WP bits 1, 2, 3, and 4 of the top column address(000000) are shifted and allocated, by a column allocation method, withemphasis being put on I/O allocation. By the I/O allocation method, withemphasis being put on column allocation, the I/Os (DQ) corresponding tothe WP bits 15, 31, 47, and 63 are skipped.

The user block is formed with 64 WP bits 0 through 63, and arebit-allocated in accordance with the correspondence relation (aconversion table) shown in FIG. 5 and the conversion table shown in FIG.6. As shown in FIGS. 5 and 6, the WP bits 0 through 63 correspond to theaddresses A17 through A20 of the DQ terminals as I/Os, and the addressesA21 and A22 as column addresses.

The factory block is a function block in which the vender maker performsrewrite, but users cannot perform rewrite. In this function block,redundant data, internal voltage trimming data, and internal timingtrimming data are written.

The factory block shown in FIG. 3 is formed with the 16 bits TR0 throughTR15 for trimming, the 32 bits of REDSECA through REDSECD for sectorredundancy, and the 128 bits of REDCOL (0-0) through REDCOL(7-1) forcolumn redundancy. Each 8 sector redundancy bits of REDSECA throughREDSECD store one defect relief address. Each 8 column redundancy bitsof REDCOL (0-0) through REDCOL (7-1) store one defect relief address.

The factory block is also allocated to DQ0 through DQ15, as shown inFIG. 3. One word line and 11 local bit lines (LBL), i.e., eleven columnaddresses (LBL4 through LBL14), are allocated to each I/O, and threeglobal bit lines (GBL) (GBL1 through GBL3) are allocated to each I/O. Asshown in FIG. 4, the factory block is also formed with 64 bits, like theuser block, and the 64 bits are allocated to DQ0 through DQ15.

FIG. 7A illustrates the structure of the CAM cell array 4 in detail, andFIG. 7B illustrates the structure of the regular cell array 3 in detail.In the CAM cell array 4 shown in FIG. 7A, the factory block and the userblock have word lines that are independent of each other, so that thefactory block is not adversely affected by the gate disturb in memoryinformation due to rewrite in the user block. In other words, differentrow addresses are allocated to the factory block and the user block. Therow decoder 5 shown in FIG. 2 allocates the CAM data of the respectivefunction blocks to the different row addresses based on externally inputaddresses. In FIG. 7A, the word line WL0 allocated to the WP bitscontained in the user block and the word lines WL1 allocated to thefactory bits contained in the factory block are shown. Further, in oneblock (the user block or the factory block), the number of word lines tobe allocated is restricted to the smallest possible number. This isbecause the structure is designed to be capable of collectively erasingthe data in one unit function block. Here, the “gate disturb” is aphenomenon in which the bit lines are connected to the same word line towhich the memory cells to be programmed are connected, and charge gainis caused due to a high voltage applied to the gates of unselectedmemory cells at the time of programming. Because of this phenomenon, thedata of the unselected memory cells change from “1 (the threshold valuebeing low)” to “0 (the threshold value being high)” due to charge gain.

Likewise, the column decoder 6 (FIG. 2) allocates the CAM data of therespective function blocks to different column addresses based onexternally input addresses. Also, address allocation is performed insuch a manner that the allocated column addresses are continuous betweenthe factory block and the user block.

So as to protect the factory block from drain disturb of the memoryinformation due to rewrite or the like performed in the user block, thebit lines of the factory block and the user block are separated fromeach other, as shown in FIG. 7A. In other words, the column decoder 6allocates column addresses that are independent of each other to theuser block and the factory block. Further, the column decoder 6allocates addresses in such a manner that the column addresses arecontinuous between the different function blocks. Here, the “bit lineseparation” indicates both the physical separation and the electricseparation of the local bit lines and the global bit lines. “Draindisturb” is a phenomenon in which the word line is connected to the samebit lines to which the memory cells to be programmed are connected, andcharge loss is caused due to a high voltage applied to the drains ofunselected memory cells at the time of programming. Because of thisphenomenon, the data of the unselected memory cells change from “0 (thethreshold value being high)” to “1 (the threshold value being low)” dueto charge loss.

Also, with all the word lines (the word lines WL1 and WL2, for example)being selected, the same column addresses are not shared between thefunction blocks, and the column addresses are made continuous betweenthe function blocks, so that all the CAM data can be read out simply byswitching the column addresses. In this manner, the time for switchingthe word lines can be saved, and CAM data can be transferred from theCAM cell array 4 to the volatile memory unit 11 (FIG. 2) in a shorttime. In such a case, when more than one word line is selected at thesame time, the bit lines to which unnecessary cell data is connected aresevered, so that the necessary cell data and the unnecessary cell datacannot be selected through the same bit line.

Taking advantage of the fact that the user block and the factory blockdo not share the same column addresses, the line pattern of the localbit lines (LBL) between the user block and the factory block isphysically cut off, and the cut-off local bit lines (LBL) are notconnected to the global bit lines (a contact via is not used, forexample). Alternatively, the user block and the factory block may beseparated from each other as sectors, and column switches for connectingwith the global bit lines are provided for the user block and thefactory block, thereby electrically severing the user block and thefactory block from each other.

With this structure, when the data is to be read from the CAM cell array4 into the volatile memory unit 11 at the time of power supply or thelike, the CAM data can be read out simply by switching the columnaddresses, with the word line of the user block and the word line of thefactory block being simultaneously selected. Since there is no need toswitch the word lines, the total time required for reading all the bitsof the CAM data can be shortened.

FIG. 9 illustrates the structures of conversion circuits that convertthe address signals for programming/erasing operations into the columnaddress signals for the respective banks. The conversion circuits areprovided in the column decoder 6 (FIG. 2). CAM program mode signals(CAMPGM) are switched between an activated state and an inactivatedstate, so that switching can be performed between a column address f theregular cell array 3 and a column address of the CAM cell array 4.

The conversion circuits include OR gates 121 to which address signalsWA(0) or WA(1) for a programming/erasing operation and a CAMPGM signalare input, OR gates 123 to which the inverted output of the CAMPGMsignal and address signals WA(21) or WA(22) are input, NAND gates 124 towhich the outputs of the OR gates 121 and 123 are input, and inverters125 that invert the outputs of the NAND gates 124. The outputs of theinverters 125 are column addresses AA(0) and AA(1). If the CAMPGM signalis in the inactivated state, the address signals WA(1) and WA(0) serveas the column addresses AA(1) and AA(0).

The conversion circuits also include OR gates 131 to which addresssignals WA(2), WA(3), WA(4), and WA(5) are input; OR gates 133 to whicha power supply voltage VCC and the inverted outputs of CAMPGM signalsare input; NAND gates 134 to which the outputs of the OR gates 131 and133 are input; and inverters 135 that invert the outputs of the NANDgates 134. The outputs of the inverters 135 serve as column addressesAA(2), AA(3), AA(4), and AA(5).

FIG. 10 illustrates conversion circuits that convert the address signalsfor programming/erasing operations into DQs. These conversion circuitsare provided as switches in the data input/output circuit 14. Theconversion circuit that generates DQ0 includes a NOR gate 142 to whichaddress signals WA(20), WA(19), WA(18), and WA(17) are input; a NANDgate 143 to which a CAMPGM signal and the output of the NOR gate 142 areinput; and an inverter 144 that inverts the output of the NAND gate 143.The conversion circuits that generate DQ1 through DQ15 also have thesame circuit structure as above.

If the CAMPGM signal is in the activated state, the address signalsWA(0) through WA(17) are allocated to CAM_DQ15 through CAM_DQ0. If theregular cell array 3 is in a selected state (i.e., the CAMPGM signal isin the inactivated state), CAM_DQ15 through CAM_DQ0 are placed in aninactivated state.

At the time of programming a write-protect bit, only the DQ to beprogrammed is activated, and applied stress, expected values, andidentification signals are controlled through the conversion circuitsshown in FIG. 10, so that the DQs not to be programmed are ignored.

Although the above described embodiment is a preferred embodiment, thepresent invention is not limited to this embodiment. For example, thefactory block may include a one-time programmable ROM (OTP ROM). An OTPROM is a functional memory a user can program only once. The OTP ROMdiffers from the factory block in terms of the function allowed tousers, but is separated from the user block in which users can performprogramming and erasing repeatedly, in view of the OTP function thatdoes not allow reprogramming. In short, it is necessary in thisstructure to also avoid gate disturb and drain disturb.

It is also possible to form the user block with a read bit block,instead of a write bit block. In such a case, read control is performedfor each desired sector.

In the above described embodiment, there is physical separation amongthe local bit lines and electrical separation from the global bit linesbetween the factory block and the user block. However, the presentinvention is not limited to this structure, and it is also possible tophysically or electrically separate the global bit lines between thefactory block and the user block.

The regular cell array and the CAM cell array may be connected so as toshare a data bus or may be connected so as to share the global bit linesof the user block and the factory block.

Also, wells may be separated or shared between the user block and thefactory block. If shared, the die size can be reduced. In such a case,floating control is performed on the word line of the factory block atthe time of performing an erasing operation in the user block.

Second Embodiment

Referring now to FIG. 11, the structure in accordance with a secondembodiment of the present invention is described. FIG. 11 illustrates acell array unit 2 (a regular cell array 3 and a CAM cell array 4) thatstore the data for a semiconductor device, a verification circuit 13that confirms a data written state or a data erased state of the cellarray 2, and expected value holding circuits 32 disposed in a datainput/output circuit 14. In this embodiment, a sixteen-bit simultaneouswrite mode is also employed so that programming can be performed throughsimultaneous access to the sixteen memory cells of the regular cellarray 3 or the CAM cell array 4.

A verification circuit 13 includes a WP bit select circuit 33 and datacomparator circuits 34. The number of expected value holding circuits 32and the number of data comparator circuits 34 disposed in the datainput/output circuit 14 are sixteen, which is the same as the number ofI/Os.

An interface mode setting signal, a signal input from each correspondingI/O, and an address signal (WP-CAM address designating signal) thatdesignates a write-protect CAM (WP-CAM) are input to the WP bit selectcircuit 33.

There are two methods of designating a CAM cell to be programmed. Inaccordance with one of the methods, the information “1” is input to theI/O corresponding to the CAM cell to be programmed while the information“0” is input to the I/Os not to be programmed (“I/O mode”). Inaccordance with the other method, the corresponding address is input tothe CAM cell to be programmed (“address mode”). The interface modesetting signal is a signal for switching the method of designating a CAMcell to be programmed between the above two methods.

FIG. 12 illustrates the structure of the WP bit select circuit 33 indetail. As shown in FIG. 12, the WP bit select circuit 33 includes adecoder 51, AND gates 53, and switches 54. The number of AND gates 53and the number of switches 54 are both sixteen, which is the same as thenumber of I/Os. With this structure, the data comparator circuit 34through which a pass is performed on pseudo verification is selected.

When the address mode is set by the interface mode setting signal, theswitches 54-(0) through 54-(15) are turned OFF and the WP-CAM addressdesignating signal is decoded by the decoder 51 to generate averification control signal. When the I/O mode is set by the interfacemode setting signal, the decoder 51 is turned OFF by the interface modesetting signal input to the decoder 51 via the inverter 52, and theswitches 54-(0) through 54-(15) are turned ON.

The signals I/O-(0) through I/O(15) from the respective I/Os andpre-read data (DAV) read out from the CAM cells in advance are input tothe AND gates 53-(0) through 53-(15), which obtains the logic productsof those signals. More specifically, if the data prior to theprogramming of the CAM cell and the data input from the I/O are both“1”, a high-level signal is output as a verification control signal. Inother cases, a low-level signal is output as a verification controlsignal.

The expected value holding circuits 32-(0) through 32-(15) are providedfor the respective I/Os, as shown in FIG. 11, and holds I/O inputinformation. The held information is output as expected value data tothe data comparator circuits 34 after programming of the regular cellarray 3. The expected value holding circuits 32-(0) through 32-(15) alsoholds information that is I/O-input at the time of programming of theCAM cell array 4 in the I/O mode. The held information is output asexpected value data to the data comparator circuits 34 after theprogramming of the CAM cell array 4. Further, the expected value holdingcircuits 32 generate expected values, with the verification controlsignal output from the WP bit select circuit 33, when the switches 35are turned ON by the interface mode setting signal at the time ofprogramming of the CAM cell array 4 in the address mode. The data isthen output as expected value data to the data comparator circuits 34after the programming of the CAM cell array 4.

The data comparator circuits 34-(0) through 34-(15) are also providedfor the respective I/Os, and compare the data read out from the regularcell array 3 or the CAM cell array 4 with the data (the expected values)stored in the expected value holding circuits 32-(0) through 32-(15). Atthe time of programming of the CAM cell array 4, the data comparatorcircuits 34 perform a pseudo-verification pass on the cells not to beprogrammed using the verification control signal from the WP bit selectcircuit 33.

Referring now to the flowchart of FIG. 13 and the diagrams of FIGS. 14Ato 14D, the operation of programming the CAM cell array 4 set in the I/Omode in accordance with this second embodiment is described. In thisembodiment, the setting of “write protect” can be performed on eachsector group consisting of sectors, where I/Os are allocated to eachsector. When a sector group in which the “write protect” is to be set isselected, protection data is programmed in the WP-CAM cell in theselected sector group.

First, CAM program setting signals (I/O-0, 1, . . . , 15) fordesignating a WP-CAM cell to be programmed are input from the respectiveI/Os (step S10). The information “1” for commanding programming is inputto the I/O corresponding to the WP-CAM cell to be programmed, and theinformation “0” for prohibiting programming is input to the other I/Os(see FIG. 14B).

The data that is already stored in the WP-CAM cells is read out inadvance (pre-read) (step S11). Judging from the pre-read data, it isdetermined whether each WP-CAM cell is in a data written state. If datahas already been written and programming has already been performed, theinformation “0” is held. If a WP-CAM cell is in an erased state withoutwritten data, the information “1” is held in the I/O (see FIG. 14A).

Next, a WP-CAM cell that is currently in an erased state and in whichwrite is allowed by the I/O input signal is detected (step S12). Morespecifically, a WP-CAM cell having pre-read data of “1”, which indicatesan erased state, and also having the I/O input of “1” is detected. Inthis detection, the expected value holding circuits 32 and the datacomparator circuits 34 shown in FIG. 11 may be used.

Programming is then performed on the detected WP-CAM cell (step S13)(see FIGS. 14C, for example). As the programming is performed, theverification circuit 13 determines whether the data has definitely beenwritten in the WP-CAM cell. At this point, the switches 35-(0) through35-(15) provided for the respective I/Os are turned OFF by the interfacemode setting signals for setting the I/O mode. The interface modesetting signal is also input to the WP bit select circuit 33, so as toturn the switches 54-(0) through 54-(15) ON.

The WP bit select circuit 33 obtains the logic products of the pre-readdata read from the WP-CAM cells and the I/O-input signals (I/O-0, 1, . .. , 15) through the AND gates 53-(0) through 53-(15) to generateverification control signals. If the I/O input is “1” commandingprogramming, and the pre-read data is “1” indicating an erased cell, ahigh-level verification control signal is output to the correspondingdata comparator circuit 34. In other cases, a low-level verificationcontrol signal is output to the corresponding data comparator circuit34.

The expected value holding circuits 32-(0) through 32-(15) latch theinput signals I/O-(0), (1), . . . , (15) as they are, and output thelatched data as DINO through DIN15 to the data comparator circuits34-(0) through 34-(15) in accordance with predetermined timing. The datais referred to as the expected value data. The verification controlsignal is input from the WP bit select circuit 33 to each of the datacomparator circuits 34-(0) through 34-(15).

The data comparator circuits 34-(0) through 34-(15) compare the dataread out from the WP-CAM cells, i.e., the data read out afterprogramming, with the expected values read out from the expected valueholding circuits 32-(0) through 32-(15). At this point, in each datacomparator circuit 34 to which a low-level verification control signalis input from the WP bit select circuit 33, comparison is not performed(step S14); instead a high-level matching signal is output so as to makea pseudo-pass for the verification (see FIG. 14D). In each datacomparator circuit 34 to which a high-level verification control signalis input from the WP bit select circuit 33, the expected value data thatis input from the corresponding expected value holding circuit 32 iscompared with the data after programming the WP-CAM cell (step S14). Ifthe I/O input is “1” commanding programming and the data read from theWP-CAM cell after programming is “1” indicating an erased state, alow-level signal indicating “Fail” is output to the determining circuit12. As shown in FIG 14D, if the I/O input is “1” and the data read fromthe WP-CAM cell after programming is “0” indicating a programmed state,a high-level signal indicating verification pass is output to thedetermining circuit 12.

When all the matching signals that are output from the data comparatorcircuits 34-(0) through 34-(15) are at the “H” level, the determiningcircuit 12 outputs a verification signal indicating data write successto the controller (step S15).

As described above, a pseudo-pass is performed on the comparison resultsof the data comparator circuits allocated to unprogrammed CAM cells inthis embodiment. Accordingly, the programming results of the programmedCAM cell can be reflected in the verification.

Referring now to the flowchart of FIG. 15 and and the diagrams of FIG.16, the operation to be performed in a case where a sector group address(SGA) is designated from the outside is described. As shown in FIG. 16,in accordance with the sequence for executing the program command of aWP-CAM cell, the procedures for command recognition are carried out infive cycles, and information is rewritten in the sixth cycle. In short,a SGA to be programmed is designated, and programming of the SGA isperformed in six cycles in total.

First, a WP-CAM address designating signal for designating a WP-CAM cellto be programmed is input. The WP-CAM address designating signal isanalyzed by the decoder (step S20), so as to generate an addresscorresponding to the WP-CAM cell to be actually programmed. In theverification circuit 13, the WP-CAM address designating signal is alsodecoded by the decoder 51 and a high-level verification control signalis output to the expected value holding circuit 32 and the datacomparator circuit 34 corresponding to the WP-CAM cell to be programmed.A low-level verification control signal is output to the other expectedvalue holding circuits 32 and the other data comparator circuits 34.

Next, the data that is already stored in the WP-CAM cell designated fromthe decoding result is pre-read (step S21). The pre-read data isanalyzed to determine the data write state of the WP-CAM cell.

If the WP-CAM cell is determined to be in an erased state (“YES” in stepS22), data is written in the WP-CAM cell and it is put into a programmedstate (step S23). If the WP-CAM cell is determined to be in a programmedstate (“NO” in step S22), the operation comes to an end.

When the programming of the WP-CAM cell is finished, verification todetermine whether the data has indeed been written in the WP-CAM cell isperformed by the verification circuit 13.

The WP bit select circuit 33 and the data comparator circuits 34-(0)through 34-(15) provided for the respective I/Os are connected withlines, and a verification control signal are output from the WP bitselect circuit 33. In the address mode, the switches 35-(0) through35-(15) are turned ON by the interface mode setting signal. Accordingly,the verification control signal is input only to the expected valueholding circuit 32 connected to the line through which a “H”-levelverification control signal is output. The expected value holdingcircuit 32 to which the “H”-level verification control signal is inputgenerates the expected value “0” indicating that the subject WP-CAM cellis programmed and outputs the expected value “0” to the data comparatorcircuit 34 (step S24) (see FIG. 16). The other expected value holdingcircuits 32 to which a “L”-level verification control signal is input donot generate an expected value (step S24). Accordingly, an expectedvalue is not output to the data comparator circuits 34.

The data comparator circuit 34 to which the expected value “0” is inputfrom the expected value holding circuit 32 reads the data from thecorresponding WP-CAM cell and compares the data DAVi with the expectedvalue “0” (denoted by /DINi in FIG. 16). Receiving the low-levelverification control signal, the other data comparator circuits 34forcibly output “H”-level matching signals. In short, a pseudoverification pass is performed (see FIG. 16).

When all the matching signals output from the data comparator circuits34 are at the “H” level, the determining circuit 12 outputs averification signal indicating data write success to the controller(step S25). The data comparison result of the actually programmed WP-CAMcell can be output as the verification result.

FIG. 17 illustrates the structures of each expected value holdingcircuit 32 and each data comparator circuit 34 shown in FIG. 11, and thestructure of the determining circuit 12. As described above, the outputof each data comparator circuit 34 is controlled by the verificationcontrol signal from the WP bit select circuit 33, and is output to thedetermining circuit 12. Also, each data comparator circuit 34 iscontrolled by a CAM mode signal for rewriting a CAM cell. Further, eachexpected value holding circuit 32 is controlled by the interface modesetting signal.

Third Embodiment

Referring now to FIG. 18, a third embodiment of the present invention isdescribed. The CAM data that is written in a CAM cell array 4 is read byswitching ON a switch 61 at the time of power supply or resetting thehardware. The CAM data is then transferred to a volatile memory 11 suchas a SRAM as shown in FIG. 18. The CAM data is read out from thevolatile memory 11 so that read access to a regular cell array 3 is notdelayed. In this embodiment, when programming is performed on the CAMs,the data stored in the volatile memory 11 is used as expected valuedata, and data comparator circuits 34 compare the expected value datawith the data that is read out from the CAM cell.

Other than the time at which verification is performed on the data thatis programmed in the CAM cell array 4, a switch 62 is switched by a CAMmode signal so as to connect the expected value holding circuits 32 tothe data comparator circuits 34. By doing so, verification using theexpected value holding circuits 32 can be performed at the time ofverifying the regular cell array 3.

FIG. 19 illustrates the structure of the WP bit select circuit 33. Inthis embodiment, the AND gates 53 of the second embodiment are notemployed. When the I/O mode is set by the interface mode setting signal,the I/O-input signals I/O (0), (1), . . . , (15) are output withoutchange as verification control signals. In the address mode, theswitches 54-(0) through 54-(15) are turned OFF, and a decoded signal isoutput from the decoder 51. When the address mode is set, a WP-CAMaddress designating signal is input to the decoder 51, which thenanalyzes the signal so as to determine the WP-CAM cell designated by theprogram. A high-level verification control signal indicating that theWP-CAM cell is designated by the programming is output to the volatilememory 11. The verification control signals that are output from theother WP-CAM cells (the WP-CAM cells that are not designated by theprogramming) are at the low level.

In the volatile memory 11, there are two memory regions that hold thedata read out from CAM cells. A first memory region is a region holdingthe data that is proved to indeed be stored in the CAM cells throughverification. In other words, the first memory region holds dataequivalent to the non-volatile memory information in the CAM cell array4 after the programming (including verification) in the CAM cells.Accordingly, when there is a request for the data of the CAM cells froma circuit required for operations at the time of a regular operation ofthe regular cell array 3, the data stored in the first memory region isoutput. A second memory region is a region that is used as a temporarymemory area and holds the data of CAM cells pre-read at the time ofprogramming.

Receiving a verification control signal from the WP bit select circuit33, the volatile memory 11 outputs “0” as the expected value of theWP-CAM cell designated by the verification control signal, as shown inFIG. 18, instead of the data that is read in at the time of pre-reading.The volatile memory 11 also outputs (initial pass) the data stored inthe second memory region at the time of pre-reading as the data of theother WP-CAM cells corresponding to low-level verification controlsignals.

Referring now to the flowchart of FIG. 20 and the illustration of FIG.21, the operation of programming the CAM cell array 4 set in the I/Omode in accordance with this third embodiment is described. First, CAMprogram setting signals (I/O-0 through I/O-15) for designating a WP-CAMcell to be programmed are input from the respective I/Os (step S30). Theinformation “1” for commanding programming is input to the I/Ocorresponding to the WP-CAM cell to be programmed and the information“0” is input to the other I/Os.

The data is then pre-read from the WP-CAM cells, and the data writestate of each WP-CAM cell is determined (step S31). If a WP-CAM cell isin a programmed state with written data, the information “0” should bestored in the WP-CAM cell. If a WP-CAM cell is in an erased statewithout written data, the information “1” should be written in theWP-CAM cell.

Next, the WP-CAM cell that is currently in an erased state and in whichwrite is allowed by an I/O input signal is detected (step S32). Morespecifically, the WP-CAM cell having the pre-read data of “1” indicatingan erased state and the I/O input of “1” is detected. In a case wherethe WP-CAM cell designated for programming has already been programmed,the operation comes to an end, and an error signal is output. Theprocedures described so far are carried out by the controller 8.

Programming is performed on the detected WP-CAM cell (step S33). As theprogramming is performed, the verification circuit 13 determines whetherthe data has definitely been written in the WP-CAM cell. At this point,the switches 54-(0) through 54-(15) provided for the I/Os are turned ONby the interface mode setting signal. The decoder 51 stops the operationupon receipt of the interface mode setting signal that is input via theinverter 52.

The WP bit select circuit 33 outputs the input signals I/O-(0) throughI/O-(15) as verification control signals to the volatile memory 11 asthey are. More specifically, as “1” is I/O-input to the WP-CAM celldesignated by the program, the WP-bit select circuit 33 outputs ahigh-level signal as the verification control signal. The verificationcontrol signals corresponding to the other WP-CAM cells are at the lowlevel.

The volatile memory 11 outputs the expected value “0” as the data of theWP-CAM cell designated by the high-level verification signal to the datacomparator circuit 34 (see FIG. 21). The pre-read data stored in thesecond memory region are output as the expected value data of the otherWP-CAM cells (see FIG. 21).

The data comparator circuits 34-(0) through 34-(15) compare the dataread from the WP-CAM cells after programming with the expected valuesread from the volatile memory 11 (step S34). Since the data read from anunprogrammed WP-CAM cell is always the same as the expected value of theWP-CAM cell, verification is performed by determining whether the dataof each programmed WP-CAM is equal to the expected value. If the dataread from the WP-CAM cell is not equal to the expected value (“NO” instep S35), the operation returns to the programming procedure (stepS33). If the data read from the WP-CAM cell is equal to the expectedvalue (“YES” in step S35), a matching signal indicating the matchingbetween the data and the expected value is output from the datacomparator circuit 34 to the determining circuit 12. If all the matchingsignals from the data comparator circuits 34 indicate the matching, thedetermining circuit 12 outputs a verification pass signal to thecontroller (step S36). If the verification succeeds, the data is readfrom the WP-CAM cell or the sense amplifier, and is stored as theauthorized data of the WP-CAM cell in the first memory region of thevolatile memory 11 (step S37).

In this embodiment, operation is controlled so as to perform a pseudopass on the comparison results of the data comparator circuits allocatedto the unprogrammed CAM cells. Accordingly, the programming result ofthe programmed CAM cell can be reflected in the verification.

Referring now to the flowchart of FIG. 22 and the diagrams of FIG. 23,the operation to be performed in the address mode is described. First, aWP-CAM address designating signal for designating a WP-CAM cell to beprogrammed is input. The WP-CAM address designating signal is analyzedby a decoder (step S40), so as to generate an address representing theWP-CAM cell to be actually programmed. In the verification circuit 13,the WP-CAM address designating signal is decoded by the decoder 51. Averification control signal for designating the WP-CAM cell to beprogrammed is then output to the volatile memory 11.

Next, the data that has already been stored in the WP-CAM cell selectedby the decoding result is read out through pre-reading (step S41). Usingthe pre-read data, the data write state of the WP-CAM cell isdetermined.

If the WP-CAM cell is determined to be in an erased state (“YES” in stepS42), data is written in the WP-CAM cell, which is thus put into aprogrammed state (step S43). If the WP-CAM cell is determined to be in aprogrammed state (“NO” in step S42), the operation comes to an end.

Thereafter, programming and verification are performed on the detectedWP-CAM cell in the same manner as in the flowchart shown in FIG. 20. Atthe time of verification, the volatile memory 11 outputs the expectedvalue “0” as the data of the WP-CAM cell designated by the high-levelverification control signal to the data comparator circuit 34 (see FIG.23). The pre-read data stored in the second memory region are output asthe expected value data of the other WP-CAM cells (see FIG. 23). Thedata comparator circuits 34-(0) through 34-(15) compare the data readfrom the WP-CAM cells after programming with the expected values readfrom the volatile memory 11 (step S44). If the data read from a WP-CAMcell after programming is equal to the expected value of the WP-CAM(“YES” in step S45), a verification pass signal is output to thecontroller 8 (step S46). If the data read from a WP-CAM cell afterprogramming is not equal to the expected value of the WP-CAM (“NO” instep S45), processing returns to program the WP-CAM cell (step S43). Ifthe verification succeeds, the data is read from the WP-CAM cell or thesense amplifier, and is stored as the proper data of the WP-CAM cell inthe first memory region of the volatile memory 11 (step S47).

FIG. 24 illustrates the structure of the verification circuit of thesemiconductor device in detail. In the verification circuit shown inFIG. 24, the inputs to each data comparator circuit 34 are switched by aCAM mode signal. More specifically, in a CAM mode, the output of thevolatile memory 11 is input to each data comparator circuit 34. In aregular operation, the outputs of the expected value holding circuits 32are input to the data comparator circuits 34.

The above described embodiments are preferred embodiments of the presentinvention. However, the present invention is not limited to theseembodiments, and various changes and modifications can be made withoutdeparting from the scope of the present invention.

For example, the volatile memory 11 may be formed with only one memoryregion (the first memory region). The CAM data written in the CAM cellarray 4 is read by switching the switch 61 at the time of power supplyor resetting the hardware. Through pre-reading, the WP-CAM cell havingthe data of “1” indicating an erased state and the I/O input of “1” isdetected by reading the information from the volatile memory 11.Programming is then performed on the detected WP-CAM cell. As theprogramming is performed, the verification circuit 13 performsverification to determine whether the data has definitely been writtenin the WP-CAM cell. The WP bit select circuit 33 outputs a high-levelsignal as a verification control signal to the WP-CAM cell designated bythe programming, and outputs low-level signals as the verificationcontrol signals to the other WP-CAM cells. The volatile memory 11outputs the expected value “0” to the data comparator circuits 34,regardless of the information stored as the data of the WP-CAM celldesignated by the high-level verification control signal in the readoutportion (not shown) of the first memory region. More simply, a clampcircuit that uses a verification control signal is attached to thereadout portion of the first memory region, so as to clamp the outputsto “0”. The information stored in the first memory region is output asthe expected value data of the other WP-CAM cells without an operationof the clamp circuit. The data comparator circuits compare the data readfrom a WP-CAM cell after programming with the expected value read fromthe volatile memory 11. If the verification result indicates “matching”,the data read from the WP-CAM cell or the sense amplifier by switchingon the switch 61, and are stored as the proper data of the WP-CAM cell.

The device components of the volatile memory 11 may include a so-calledstatic memory cell, or may be a latch circuit that is formed with logicelements applied to the peripheral circuits.

Although a few preferred embodiments of the present invention have beenshown and described, it would be appreciated by those skilled in the artthat changes may be made in these embodiments without departing from theprinciples and spirit of the invention, the scope of which is defined inthe claims and their equivalents.

1. A semiconductor device comprising: a cell array that stores operationsetting information for the semiconductor device; and a control unitthat controls read and write operations to be performed on the cellarray, the control unit allocating different row addresses forrespective functions of the operation setting information.
 2. Thesemiconductor device as claimed in claim 1, wherein the control unitallocates different column addresses for the respective functions of theoperation setting information.
 3. The semiconductor device as claimed inclaim 1, wherein the control unit allocates continuous column addressesfor the respective functions of the operation setting information. 4.The semiconductor device as claimed in claim 1, wherein the control unitallocates the operation setting information to column addresses selectedby one of the row addresses.
 5. The semiconductor device as claimed inclaim 1, wherein the control unit allocates the operation settinginformation to all I/Os of an arbitrary column selected by the rowaddress.
 6. The semiconductor device as claimed in claim 1, whereinmemory cells accessed by different row addresses are isolated from eachother in terms of wiring pattern of local bit lines.
 7. Thesemiconductor device as claimed in claim 1, wherein memory cells areconnected to switches for selectively connecting the memory cells to bitlines arranged on a corresponding column.
 8. The semiconductor device asclaimed in claim 1, wherein, the cell array comprises cells for eachcolumn, and memory cells not storing the operation setting informationare isolated from bit lines arranged on a corresponding column.
 9. Thesemiconductor device as claimed in claim 3, wherein the control unitselects all word lines on the cell array, and reads the operationsetting information data from the cell array while successively changingthe column addresses.
 10. The semiconductor device as claimed in claim1, wherein the control unit comprises a table that converts the numberof a designated memory cell into an address of a corresponding memorycell.
 11. A method of allocating addresses to a cell array that storesoperation setting information as to a semiconductor device, the methodcomprising the step of: allocating different row addresses to respectivefunctions of the operation setting information.
 12. The method asclaimed in claim 11, further comprising the step of: allocatingdifferent column addresses for the respective functions of the operationsetting information.
 13. The method as claimed in claim 11, furthercomprising the step of: allocating continuous column addresses for therespective functions of the operation setting information.
 14. Themethod as claimed in claim 13, further comprising the step of: selectingall word lines on the cell array and successively changing the columnaddresses to read data from the cell array.
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